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0.8% Accurate Quad UV/OV Positive/Negative Voltage Supervisor ADM12914
FEATURES
Quad undervoltage/overvoltage (UV/OV) positive/negative supervisor Supervises up to two negative rails Adjustable UV and OV input thresholds Industry leading threshold accuracy over the extended temperature range: 0.8% 1 V buffered reference output Open-drain UV and OV reset outputs Adjustable reset timeout with disable option Outputs guaranteed down to VCC of 1 V Glitch immunity 62 A supply current 16-lead QSOP package Specified from -40C to +125C
FUNCTIONAL BLOCK DIAGRAM
VCC TIMER
ADM12914
VH1 TIMER 500mV VL1 VH2 UV 500mV VL2 VH3 500mV OV VL3 VH4 500mV VL4 SEL GND MUX
OUTPUT LOGIC
APPLICATIONS
Server supply monitoring FPGA/DSP core and I/O voltage monitoring Telecommunications equipment Medical equipment
LOGIC REF
LATCH/DIS REF
08265-001
Figure 1.
GENERAL DESCRIPTION
The ADM12914 is a quad voltage supervisory IC ideally suited for monitoring multiple rails in a wide range of applications. Each monitored rail has two dedicated input pins, VHx and VLx, which allows each rail to be monitored for both undervoltage (UV) and overvoltage (OV) conditions with high threshold accuracy of 0.8%. Common active low undervoltage (UV) and overvoltage (OV) pins are shared by each of the monitored voltage rails. The ADM12914 includes a 1 V buffered reference output, REF, that acts as an offset when monitoring a negative voltage. The three-state SEL pin determines the polarity of the third and fourth inputs, that is, it configures the device to monitor positive or negative supplies. The device incorporates an internal shunt regulator that enables the device to be used in higher voltage systems. This feature
requires a resistor to be placed between the main supply rail and the VCC pin to limit the current flow into the VCC pin at a level no greater than 10 mA. The ADM12914 uses the internal shunt regulator to regulate VCC if the supply line exceeds the absolute maximum ratings. The ADM12914 is available in two models. The ADM12914-1 offers a latching overvoltage output that can be cleared by toggling the LATCH input pin. The ADM12914-2 has a disable pin that can override and disable both the UV and the OV output signals. The ADM12914 is available in a 16-lead QSOP package. The device is specified over the extended temperature range of -40C to +125C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADM12914 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution .................................................................................. 4 Pin Configurations and Function Descriptions ........................... 5 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 9 Voltage Supervision ...................................................................... 9 Polarity Configuration ................................................................. 9 Monitoring Pin Connections .................................................... 10 Threshold Accuracy ................................................................... 10 Voltage Monitoring Example .....................................................11 Power-Up and Power-Down ..................................................... 12 UV/OV Timing Characteristics ............................................... 12 Timer Capacitor Selection ........................................................ 12 UV and OV Rise and Fall Time ................................................ 13 UV/OV OUTPUT Characteristics ........................................... 13 Glitch Immunity ......................................................................... 13 Undervoltage Lockout (UVLO) ............................................... 13 Shunt Regulator .......................................................................... 13 OV Latch (ADM12914-1) ......................................................... 13 Disable (ADM12914-2) ............................................................. 13 Typical Applications ....................................................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
9/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM12914 SPECIFICATIONS
TA = -40C to +125C. Typical values at TA = 25C, unless otherwise noted. VCC = 3.3 V, VLx = 0.45 V, VHx = 0.55 V, LATCH = VCC, SEL = VCC, DIS = open, unless otherwise noted. Table 1.
Parameter SHUNT REGULATOR VCC Shunt Regulator Voltage VCC Shunt Regulator Load Regulation SUPPLY Supply Voltage 1 Minimum VCC Output Valid Supply Undervoltage Lockout Supply Undervoltage Lockout Hysteresis Supply Current REFERENCE OUTPUT Reference Output Voltage UNDERVOLTAGE/OVERVOLTAGE CHARACTERISTICS Undervoltage/Overvoltage Threshold Undervoltage/Overvoltage Threshold to Output Delay VHx, VLx Input Current UV/OV Timeout Period OV LATCH CLEAR INPUT OV Latch Clear Threshold Input High OV Latch Clear Threshold Input Low LATCH Input Current DISABLE INPUT DIS Input High DIS Input Low DIS Input Current TIMER CHARACTERISTICS TIMER Pull-Up Current TIMER Pull-Down Current TIMER Disable Voltage OUTPUT VOLTAGE Output Voltage High UV/OV Output Voltage Low UV/OV THREE-STATE INPUT SEL Low Level Input Voltage High Level Input Voltage Pin Voltage when Left in High-Z State SEL High, Low Input Current Maximum SEL Input Current
1
Symbol VSHUNT VSHUNT VCC VCCR(MIN) VCC(UVLO) VCC(HYST) ICC VREF VUOT tUOD IVHL tUOTO VLATCH(IH) VLATCH(IL) ILATCH VDIS(IH) VDIS(IL) IDIS ITIMER(UP) ITIMER(DOWN) VTIMER(DIS) VOH VOL
Min 6.3
Typ 6.6
Max 6.8 150 VSHUNT 0.9 2.06 35 100 1.008 504 350 10 10.5
Unit V mV V V V mV A V mV s nA ms V
Test Conditions/Comments ICC = 5 mA ICC = 2 mA to 10 mA
2.3 1.94 15 2 25 62 1 500 200 8.5
DIS = 0 V DIS = 0 V, VCC rising DIS = 0 V VCC = 2.3 V to 6.0 V IVREF = 1 mA VCC = 2.3 V to 6.0 V VHx = VUOT - 5 mV or VLx = VUOT + 5 mV CTIMER = 1 nF
0.994 496 100 7.5 1.2
0.8 50 1.2 1.25 -1.7 1.7 -180 1 0.1 0.01 0.3 0.15 0.4 1.4 0.8 0.9 1.0 25 30 2 -2.1 2.1 -270 0.8 2.75 -2.5 2.5
V nA V V A A A mV V V V V V V A A VLATCH > 0.5 V
VDIS > 0.5 V VTIMER = 0 V VTIMER = 1.6 V Referenced to VCC VCC = 2.3 V; IUV/OV = -1 A VCC = 2.3 V; IUV/OV = 2.5 mA VCC = 0.9 V; IUV = 100 A
VIL VIH VZ ISEL ISEL(MAX)
ISEL = 10 A SEL tied to VCC or GND
The maximum voltage on the VCC pin is limited by the input current. The VCC pin has an internal 6.5 V shunt regulator and, therefore, a low impedance supply exceeding 6 V may exceed the maximum allowable input current. When operating from a higher supply than 6 V, always use a dropping resistor.
Rev. 0 | Page 3 of 16
ADM12914 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC UV, OV TIMER VLx, VHx, LATCH, DIS, SEL ICC Reference Load Current (IREF) IUV, IOV Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Rating -0.3 V to +6 V -0.3 V to +16 V -0.3 V to (VCC + 0.3 V) -0.3 V to +7.5 V 10 mA 1 mA 10 mA -65C to +150C -40C to +125C 300C
Table 3. Thermal Resistance
Package Type 16-Lead QSOP JA 104 Unit C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 4 of 16
ADM12914 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VH1 1 VL1 2 VH2 3 VL2 4 VH3 5 VL3 6 VH4 7 VL4 8
16 15
VCC TIMER SEL LATCH UV OV
08265-002
VH1 1 VL1 2 VH2 3 VL2 4 VH3 5 VL3 6 VH4 7 VL4 8
16 15
VCC TIMER SEL DIS UV OV GND
08265-011
ADM12914-1
TOP VIEW (Not to Scale)
14 13 12 11 10 9
ADM12914-2
TOP VIEW (Not to Scale)
14 13 12 11 10 9
REF GND
REF
Figure 2. ADM12914-1 Pin Configuration
Figure 3. ADM12914-2 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. ADM12914-1 1, 3 2, 4 5, 7 ADM12914-2 1, 3 2, 4 5, 7 Mnemonic VH1, VH2 VL1, VL2 VH3, VH4 Description Voltage High Input 1 and Voltage High Input 2. If the voltage monitored by VH1 or VH2 drops below 0.5 V an undervoltage condition is detected. Connect to VCC when not in use. Voltage Low Input 1. If the voltage monitored by VL1 or VL2 rises above 0.5 V an overvoltage condition is detected. Tie to GND when not in use. Voltage High Input 3 and Voltage High Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VH3 and VH4 drops below 0.5 V, an undervoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input drops below 0.5 V, an overvoltage condition is detected. Connect to VCC when not in use. Voltage Low Input 3 and Voltage Low Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VL3 or VL4 rises above 0.5 V, an overvoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input rises above 0.5 V, an undervoltage condition is detected. Tie to GND when not in use. Device Ground. Buffered Reference Output. This pin is a 1 V reference that is used as an offset when monitoring negative voltages. This pin can source or sink 1 mA, and drive loads up to 1 nF. Larger capacitive loads may lead to instability. Leave unconnected when not in use. Overvoltage Reset Output. OV is asserted low if a negative polarity input voltage drops below its associated threshold or if a positive polarity input voltage exceeds its threshold. The ADM12914-1 allows OV to be latched low. The ADM12914-2 holds OV low for an adjustable timeout period determined by the timer capacitor. This pin has a weak pull-up to VCC and can be pulled up to 16 V externally. Leave this pin unconnected when not in use Undervoltage Reset Output. UV is asserted low if a negative polarity input voltage exceeds its associated threshold or if a positive polarity input voltage drops below its threshold. UV is held low for an adjustable timeout period set by the external capacitor tied to the TIMER pin. The UV pin has a weak pull-up to VCC and can be pulled up to 16 V externally via an external pull-up resistor. Leave this pin unconnected when not in use. OV Latch Bypass Input/Clear Pin. When pulled high, the OV latch is cleared. When held high, the OV output has the same delay and output characteristics as the UV output. When pulled low, the OV output is latched when asserted. (Applies only to the ADM12914-1.) OV and UV Disable Input. When pulled high, the OV and UV outputs are held high irrespective of the state of the VHx and VLx input pins. However, if a UVLO condition occurs, the OV and UV outputs are asserted. This pin has a weak internal pull-down (2 A) to GND. Leave this pin unconnected when not in use. (Applies only to the ADM12914-2.) Input Polarity Select. This three-state input pin allows the polarity of VH3, VL3, VH4, and VL4 to be configured. Connect this pin to VCC or GND, or leave it open to select one of three possible input polarity configurations (see Table 5).
Rev. 0 | Page 5 of 16
6, 8
6, 8
VL3, VL4
9 10
9 10
GND REF
11
11
OV
12
12
UV
13
N/A 1
LATCH
N/A1
13
DIS
14
14
SEL
ADM12914
Pin No. ADM12914-1 15 ADM12914-2 15 Mnemonic TIMER Description Adjustable Reset Delay Timer. Connect an external capacitor to the TIMER pin to program the reset timeout delay. Refer to Figure 15 in the Typical Performance Characteristics section. Connect this pin to VCC to bypass the timer. Supply Voltage. VCC operates as a direct supply for voltages up to 6 V. For voltages greater than 6 V, it operates as a shunt regulator. A dropping resistor must be used in this configuration to limit the current to less than 10 mA. When used without the resistor, the voltage at this pin must not exceed 6 V. A 0.1 F bypass capacitor or greater should be used.
16
16
VCC
1
N/A means not applicable.
Rev. 0 | Page 6 of 16
ADM12914 TYPICAL PERFORMANCE CHARACTERISTICS
0.505 0.504
THRESHOLD VOLTAGE, VUOT (V)
6.80 6.75 6.70
0.503 0.502 0.501
VCC (V)
6.65 6.60 6.55 6.50 6.45
08265-012
0.500 0.499 0.498 0.497 0.496 0.495 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
-40C +25C
+85C
0
2
4 ICC (mA)
6
8
10
Figure 4. Input Threshold Voltage vs. Temperature
90 85 80 75 VCC = 3.3V 1.020 1.015
Figure 7. VCC Shunt Voltage vs. ICC
REFERENCE VOLTAGE, VREF (V)
VCC = 6V
1.010 1.005 1.000 0.995 0.990 0.985
08265-016
08265-017
ICC (A)
70 65 60 55
08265-013
VCC = 2.3V
50 -40
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110
125
0.980 -40
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110
125
Figure 5. Supply Current vs. Temperature
6.80 6.75 6.70 6.65
VCC (V) 1000
Figure 8. Buffered Reference Voltage vs. Temperature
TRANSIENT DURATION (s)
200A 1mA 2mA 5mA 10mA
900 800 700 600 500 400 300 200 100 VCC = 2.3V VCC = 6V
RESET ASSERTED ABOVE THE LINE
6.60 6.55 6.50 6.45
08265-014
6.40 -40
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110
125
0 0.1
1 10 COMPARATOR OVERDRIVE (% OF VUOT)
100
Figure 6. VCC Shunt Voltage vs. Temperature
Figure 9. Transient Duration vs. Comparator Overdrive
Rev. 0 | Page 7 of 16
08265-015
6.40
ADM12914
14 13 PULL-DOWN CURRENT IUV (mA) 12 11 10 9 8 7 -40
3.0 2.5 2.0 1.5 1.0
VHx = 0.45V SEL = VCC
UV/OV TIMEOUT PERIOD, tUOTO (ms)
UV = 150mV
UV = 50mV 0.5 0
08265-018
-25
-10
5
20
35
50
65
80
95
110
125
0
1
TEMPERATURE (C)
2 3 4 SUPPLY VOLTAGE, VCC (V)
5
6
Figure 10. UV/OV Timeout Period vs. Temperature
0.9 0.8 0.7 0.6 WITH 10k PULL-UP
Figure 13. ISINK, IUV vs. VCC
1000 900 800 700
UV/OV, VOL (mV)
+85C
UV VOLTAGE (V)
0.5 0.4 0.3 0.2 0.1 0 -0.1 0 0.1 0.2 WITHOUT PULL-UP
600 500 400 - 40C 300 200 100
+25C
08265-019
0.3 0.4 0.5 0.6 0.7 SUPPLY VOLTAGE, VCC (V)
0.8
0.9
1.0
0
5 ISINK (mA)
10
15
Figure 11. UV Output Voltage vs. VCC
5.0
UV/OV TIMEOUT PERIOD, tUOTO (ms)
Figure 14. UV/OV Voltage Output Low vs. Output Sink Current
10k
4.5 4.0 3.5
UV VOLTAGE (V)
VHx = 0.55V SEL = VCC
1k
3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 SUPPLY VOLTAGE, VCC (V) 4 5
08265-020
100
10
1 10 100 TIMER PIN CAPACITANCE CTIMER (nF)
1000
Figure 12. UV Output Voltage vs. VCC
Figure 15. UV/OV Timeout Period vs. Capacitance
Rev. 0 | Page 8 of 16
08265-023
0
1 0.1
08265-022
0
08265-021
-0.5
ADM12914 THEORY OF OPERATION
VOLTAGE SUPERVISION
The ADM12914 supervises up to four voltage rails for undervoltage and overvoltage conditions. Two pins, VHx and VLx, are assigned to monitor each rail, one for overvoltage detection and the other for undervoltage detection. Each pin is connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 0.5 V voltage reference with very high threshold accuracy of 0.8%. The device is specified over the extended operating temperature range from -40C to +125C. The output of each of the internal undervoltage comparators is tied to a common UV output pin. Likewise, the outputs of the internal overvoltage comparators are tied to a common OV output pin.
PSU 5V 3.3V 2.5V 1.8V
POLARITY CONFIGURATION
The ADM12914 is capable of monitoring supply voltages of both positive and negative polarities. The SEL pin is a threestate pin that determines the polarity of Input 3 and Input 4. As summarized in Table 5, the SEL pin is connected to either GND or VCC, or is not connected. When an input is configured to monitor a positive voltage, using the three resistor scheme that is shown in Figure 17, VHx is connected to the high-side tap of the resistor divider and VLx is connected to the low-side tap of the resistor divider. Conversely, when an input is configured to monitor a negative voltage, UVx and OVx are swapped internally. The negative voltage for monitoring is then connected as shown in Figure 18. VHx remains connected to the high-side tap and VLx remains connected to the low-side tap. Within this configuration, an undervoltage condition occurs when the monitored voltage is less negative than the programmed threshold, and an overvoltage condition occurs when the monitored voltage is more negative than the programmed threshold.
VH1 VL1 VH2
VCC
SEL TIMER SYSTEM
ADM12914
VL2 VH3 VL3 VH4 VL4 REF LATCH/DIS UV OV
GND
08265-003
Figure 16. Typical Applications Diagram
Table 5. Polarity Configuration
Input 3 SEL Pin Connected to VCC Left Unconnected Connected to GND Polarity Positive Positive Negative UV Condition VH3 < 0.5 V VH3 < 0.5 V VL3 > 0.5 V OV Condition VL3 > 0.5 V VL3 > 0.5 V VH3 < 0.5 V Polarity Positive Negative Negative Input 4 UV Condition VH4 < 0.5 V VL4 > 0.5 V VL4 > 0.5 V OV Condition VL4 > 0.5 V VH4 < 0.5 V VH4 < 0.5 V
Rev. 0 | Page 9 of 16
ADM12914
MONITORING PIN CONNECTIONS
Positive Voltage Monitoring Scheme
When monitoring a positive supply, the desired nominal operating voltage for monitoring is denoted by VM, IM is the nominal current through the resistor divider, VOV is the overvoltage trip point, and VUV is the undervoltage trip point.
VM RX VPH VHx RY UVx 0.5V
When RY and RZ are known, RX is calculated using the following formula:
RX =
(V M ) -R -R (I M ) Z Y
(3)
If VM, IM, VOV, or VUV change, each step must be recalculated.
Negative Voltage Monitoring Scheme
Figure 18 shows the circuit configuration for negative supply voltage monitoring. To monitor a negative voltage, a 1 V reference voltage is required to connect to the end node of the voltage divider circuit. This reference voltage is generated internally and is output through the REF pin.
REF
ADM12914
OVx VPL
08265-004
ADM12914
RZ
VLx
RZ VNH VHx RY OVx 0.5V
Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration
Figure 17 illustrates the positive voltage monitoring input connection. Three external resistors, RX, RY, and RZ, divide the positive voltage for monitoring,VM, into high-side voltage, VPH, and low-side voltage, VPL. The high-side voltage is connected to the corresponding VHx pin and the low-side voltage is connected to the corresponding VLx pin. To trigger an overvoltage condition, the low-side voltage (in this case, VPL) must exceed the 0.5 V threshold on the VLx pin. The low-side voltage, VPL, is given by the following equation:
UVx VNL RX VM VLx
08265-005
Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration
RZ V PL = VOV R +R +R Y Z X
Also,
= 0.5 V
The equations described previously in the Positive Voltage Monitoring Scheme section need some minor modifications for use with negative voltage monitoring. The 1 V reference voltage is added to the overall voltage drop; it must therefore be subtracted from VM, VUV, and VOV before using each in the previous equations. To monitor a negative voltage level, the resistor divider circuit divides the voltage differential level between the 1 V reference voltage and the negative supply voltage into high-side voltage, VNH, and low-side voltage, VNL. Similar to the positive voltage monitoring scheme, the high-side voltage, VNH, is connected to the corresponding VHx pin and the low-side voltage, VNL, is connected to the corresponding VLx pin. Refer to the Voltage Monitoring Example section for further information.
V R X + RY + R Z = M IM
Therefore, RZ, which sets the desired trip point for the overvoltage monitor, is calculated using the following equation:
RZ = (0.5)(V M ) (VOV )(I M ) (1)
To trigger the undervoltage condition, the high-side voltage, VPH, must exceed the 0.5 V threshold on the VHx pin. The highside voltage, VPH, is given by the following equation:
RY + R Z V PH = VUV R +R +R Y Z X
(0.5)(V M ) -R (VUV )(I M ) Z
THRESHOLD ACCURACY
The reset threshold accuracy is fundamental, especially at lower voltage levels. Consider an FPGA application that requires a 1 V core voltage input with a tolerance of 5%, where the supply has a specified regulation, for example, 2.6%. As shown in Figure 19, to ensure the supply is within the FPGA input voltage requirement range, its voltage level must be monitored for UV and OV conditions. The voltage swing on the supply itself causes the voltage band available for setting the monitoring threshold to be quite narrow. In this example, the threshold voltages, including the
= 0. 5 V
Because RZ is already known, RY can be expressed as follows:
RY =
(2)
Rev. 0 | Page 10 of 16
ADM12914
tolerances, must fit within a monitor region of just 0.024 V. The ADM12914 device with 0.1% resistors can achieve this level of accuracy.
VOLTAGE 1.05V
+5% TOLERANCE
The four worst-case scenarios of minimum and maximum undervoltage and overvoltage thresholds are calculated as follows: Minimum overvoltage threshold
(R - 0.1%) + (RY - 0.1%) VOV _ MIN = (0.5V - 0.8%)1 + X (R Z + 0.1%)
2.4% RANGE FOR OV MONITORING +2.6% SUPPLY REGULATION -2.6% SUPPLY REGULATION 2.4% RANGE FOR UV MONITORING
1.026V 1V CORE VOLTAGE 0.974V 0.95V UV
-5% TOLERANCE
(96,500 + 7410)(0.999) = 0.4961 + (96,500)(1.001) =1.029 V > 1.026 V Maximum overvoltage threshold
tUOTO
TIME
08265-006
(R + 0.1%) + (RY + 0.1%) VOV _ MAX = (0.5 V + 0.8%)1 + X (RZ - 0.1%)
Figure 19. Monitoring Accuracy Example
VOLTAGE MONITORING EXAMPLE
To illustrate how the ADM12914 device works in a real-world application, consider the 1 V input example shown in Figure 19, with the addition of a -5 V rail. The first step is to choose the current flow through both voltage divider circuits, for example, 5 A. For the 1 V 5% input, due to the specified 2.6% regulation of the supply, the UV and OV threshold should be set in the middle of the undervoltage and overvoltage monitoring bands, respectively; in this case, on the 3.8% points of the supply, which are 0.962 V for the UV threshold and 1.038 V for OV threshold. Input these values into Equation 1 to Equation 3 as follows:
RZ = (0.5)(1) 96.5 k (1.038)(5 x 10 -6 )
= 1.047 V < 1.05 V The maximum and minimum overvoltage threshold values reside within the 1.026 V to 1.05 V range specified. The minimum and maximum undervoltage thresholds are calculated as follows: Minimum undervoltage threshold
(R X - 0.1%) VUV _ MIN = (0.5 V - 0.8%)1 + (R + 0.1%) + (R + 0.1%) Y Z
= 0.9557 V > 0.95 V Maximum undervoltage threshold (R X + 0.1%) VUV _ MAX = (0.5 V + 0.8%)1 + (R - 0.1%) + (R - 0.1%) Y Z = 0.9729 V < 0.974 V These values fit within the specified undervoltage monitoring range. All four worst-case scenarios satisfy the tolerance requirement; therefore, the design approach is valid.
-5V RAIL 1V RAIL 5V
(1)
Insert the value of RZ into Equation 2.
RY = (0.5)(1) - 96.5 k 7.41 k (0.962)(5 x 10 -6 )
(2)
Then substitute the calculated values for RZ and RY into Equation 3.
RX = 1 - 96.5 k - 7.41 k 96.5 k 5 x 10 -6 (3)
96.5k VH1 7.41k VL1 96.5k 1.09M VL3 14.3k VH3 93.1k REF
VCC
OV UV
This design approach meets the application specifications. As described previously, the 1 V rail is specified with an input requirement of 5% and a supply tolerance of 2.6%. This effectively means the OV threshold of the monitoring device, including all the tolerance factors, must fit within the 1.026 V to 1.05 V range. Similarly, the UV threshold range must be between 0.95 V and 0.974 V.
ADM12914
SEL GND
08265-007
Figure 20. Positive and Negative Supply Monitor Example
Rev. 0 | Page 11 of 16
ADM12914
Next, consider a -5 V input, which is specified with a 12% input. The threshold accuracy required by the supply is chosen to be within 5% of the -5 V rail. The UV and OV threshold should be set in the middle of the undervoltage and overvoltage monitoring bands, respectively. In this case, on the 8.5% points of the supply, which is -4.575 V for the UV threshold and -5.425 V for the OV threshold. The negative voltage scheme configuration requires that the 1 V reference voltage be accounted for in Equation 1 to Equation 3. The 1 V reference voltage is subtracted from VM, VUV, and VOV, and the absolute value of the result is taken. Equation 1 becomes
TIMER CAPACITOR SELECTION
The UV and OV timeout period on the ADM12914 is programmable via the external timer capacitor, CTIMER, placed between the TIMER pin and ground. The timeout period, tUOTO, is calculated using the following equation:
CTIMER = (tUOTO)(115)(10-9) F/sec
RZ =
( - 5.425 - 1 )(5 x 10 - 6
(0.5) - 5 - 1
(0.5)( - 5 - 1 )
Refer to Figure 15 in the Typical Performance Characteristics section, which illustrates the delay time as a function of the timer capacitor value. A minimum capacitor value of 10 pF is required. The chosen timer capacitor must have a leakage current that is less than the 1.7 A TIMER pin charging current. To bypass the timeout period, connect the TIMER pin to VCC.
VHx MONITOR TIMING VHx VUOT
) 93.1 k
Insert the value of RZ into Equation 2 RY =
( - 4.575 - 1 )(5 x10 -6 )
(
)
tUOD
tUOTO
- 93.1 k 14.3 k
UV 1V
To calculate RX, insert the value of RZ and RY into Equation 3.
RX =
( - 5 -1 ) ( - 14.3 k ) - (93.1 k ) 1.09 M -6
5 x 10
VHx VUOT tUOD
VHx MONITOR TIMING (TIMER PIN TIED TO VCC)
POWER-UP AND POWER-DOWN
On power-up, when VCC reaches 1 V, the active low UV output asserts and the OV output pulls up to VCC. When the voltage on the VCC pin reaches 1 V, the ADM12914 is guaranteed to assert UV low and OV high. When VCC exceeds 1.9 V (minimum), the VHx and VLx inputs take control. When VCC and each of the VHx inputs are valid, an internal timer begins. Subsequent to an adjustable time delay, UV weakly pulls high.
tUOD
UV
1V
08265-026
08265-027
NOTES 1. WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VHx TRIGGERS AN OVERVOLTAGE CONDITION.
Figure 21. VHx Positive Voltage Monitoring Timing Diagrams
VLx MONITOR TIMING VLx
UV/OV TIMING CHARACTERISTICS
UV is an active low output. It asserts when any of the four monitored voltages is below its associated threshold. When the voltage on the VCC pin is greater than 2 V, an internal timer holds UV low for an adjustable period, tUOTO, after the voltages on all the monitoring rails rise above their thresholds. This allows time for all monitored power supplies to stabilize after power-up. Similarly, any monitored voltage that falls below its threshold initiates a timer reset, and the internal timer restarts once all the monitoring rails rise above their thresholds. The UV and OV outputs are held asserted after all faults have cleared for an adjustable timeout period, determined by the value of the external capacitor attached to the TIMER pin.
VUOT tUOD tUOTO
OV
1V
VLx MONITOR TIMING (TIMER PIN TIED TO VCC) VLx VUOT tUOD tUOD
OV
1V
NOTES 1. WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VLx TRIGGERS AN UNDERVOLTAGE CONDITION.
Figure 22. VLx Positive Voltage Monitoring Timing Diagrams
Rev. 0 | Page 12 of 16
ADM12914
UV AND OV RISE AND FALL TIMES
The UV or OV output rise times (from 10% to 90%) can be approximated using the following equation:
tR 2.2(RPULL-UP)(CLOAD)
UNDERVOLTAGE LOCKOUT (UVLO)
The ADM12914 has an undervoltage lockout circuit that monitors the voltage on the VCC pin. When the voltage on VCC drops below 1.94 V (minimum), the circuit activates. The UV output is asserted and the OV output is cleared and is not allowed to assert. When VCC recovers, UV exhibits the same timing characteristics as though an undervoltage condition had occurred on the inputs.
where: RPULL-UP is the internal weak pull-up resistance with an approximate value of 400 k at room temperature with VCC > 1 V. CLOAD is the external load capacitance on the output pin. When a fault occurs, the UV or OV output fall time can be expressed as
tF 2.2(RPULL-DOWN)(CLOAD)
SHUNT REGULATOR
The ADM12914 is powered via the VCC pin. The VCC pin can be directly connected to a voltage rail of up to 6 V. In this mode, the supply current of the device does not exceed 100 A. An internal shunt regulator allows the ADM12914 to operate at higher input voltage levels by placing a shunt resistor in series between the supply rail and the VCC pin to limit the input current to less than 10 mA. Use Figure 7 in the Typical Performance Characteristics section to assist in determining the value of this resistance. Choose an appropriate location on the curve to accommodate variations in VCC due to changes in current through the dropper resistor.
where RPULL-DOWN is the internal pull-down resistance, which is approximately 50 . Assuming a load capacitance of 150 pF, the fall time is 16.5 ns.
UV/OV OUTPUT CHARACTERISTICS
Both the OV and UV outputs have strong pull-down to ground and weak internal pull-up to VCC. This permits the pins to behave as open-drain outputs. When the rise time on the pin is not critical, the weak pull-up removes the requirement for an external pull-up resistor. The open-drain configuration allows for wire-OR'ing of outputs, which is particularly useful when more than one signal needs to pull down on the output. At VCC = 1 V, a maximum VOL = 0.15 V at UV is guaranteed. At VCC = 1 V, the weak pull-up current on OV is almost turned on. Consequently, if the state and pull-up strength of the OV pin is important at very low VCC, an external pull-up resistor of no more than 100 k is advised. By adding an external pull-up resistor, the pull-up strength on the OV pin is greater. Therefore, if it is connected in a wire-OR'ed configuration, the pull-down strength of any single device must account for this additional pull-up strength.
OV LATCH (ADM12914-1)
If an overvoltage condition occurs when the LATCH pin is pulled low, the OV pin latches low. Pulling LATCH high clears the latch. If an OV condition clears while LATCH is high, the latch is bypassed and the OV pin behaves in the same way as the UV pin, with an identical timeout period. If the LATCH pin is pulled low while the timeout period is active, the OV pin latches low, as in normal operation.
DISABLE (ADM12914-2)
Pulling the DIS pin high disables both the UV and OV outputs, and forces both outputs to remain weakly pulled high, regardless of any faults that are detected at the inputs. If a UVLO condition is detected, the UV output is asserted and pulls low; however, the timeout function is bypassed. As soon as the UVLO condition clears, the UV output pulls high. To guarantee normal operation when the pin is left unconnected, DIS has a weak 2 A internal pull-down current.
GLITCH IMMUNITY
The ADM12914 is immune to short transients that may occur on the monitored voltage rails. The device contains internal filtering circuitry that provides immunity to fast transient glitches. Figure 9 illustrates glitch immunity performance by showing the maximum transient duration without causing a reset pulse. Glitch immunity makes the ADM12914 suitable for use in noisy environments.
Rev. 0 | Page 13 of 16
ADM12914 TYPICAL APPLICATIONS
PSU 5V 3.3V 2.5V 1.8V 312k VH1 2.37k 200k VL1 VH2 33.6k 2.34k 111k VL2 VH3 34.8k 1.82k 120k VL3 VH4 27.1k 3.05k VL4 LATCH/DIS OV UV TIMER SYSTEM VCC SEL
ADM12914
45.3k
REF
GND
08265-008
Figure 23. Typical Application Diagram for Monitoring 5 V, 3.3 V, 2.5 V, and 1.8 V with 1.5% Supply Tolerance and 5% Input Tolerance Requirement
+12V PSU -12V 1.98M VH1 5.62k VL1 VH2 83.5k VL2 VH3 51.7k VL3 VH4 12k VL4 1420k REF GND
08265-009
1k
VCC
SEL TIMER SYSTEM
ADM12914
UV OV
LATCH/DIS
Figure 24. Typical Application Diagram for Monitoring 12 V with 1.5% Supply Tolerance and 5% Input Tolerance Requirement; -12 V with 3% Supply Tolerance and 15% Input Tolerance Requirement
Rev. 0 | Page 14 of 16
ADM12914 OUTLINE DIMENSIONS
0.197 (5.00) 0.193 (4.90) 0.189 (4.80)
16
9
1
0.158 (4.01) 0.154 (3.91) 0.150 (3.81)
8
0.244 (6.20) 0.236 (5.99) 0.228 (5.79)
0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10)
0.069 (1.75) 0.053 (1.35) SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8 0
0.010 (0.25) 0.006 (0.15)
0.020 (0.51) 0.010 (0.25)
0.025 (0.64) BSC
0.050 (1.27) 0.016 (0.41)
0.041 (1.04) REF
COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012808-A
Figure 25. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model ADM12914-1ARQZ 1 ADM12914-1ARQZ-RL71 ADM12914-2ARQZ1 ADM12914-2ARQZ-RL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP]
Package Option RQ-16 RQ-16 RQ-16 RQ-16
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
ADM12914 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08265-0-9/09(0)
Rev. 0 | Page 16 of 16

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